1. Field of the Invention
The present invention relates to a manufacturing method for a semiconductor device while detecting the position of each semiconductor element using an alignment mark.
2. Description of the Related Art
With portable electronic appliances such as mobile phones, PDAs, DVCs and DSCs becoming more and more advanced in their capabilities, miniaturization and weight reduction of products have become essential for market acceptance. Accordingly, highly-integrated system LSIs for achieving these goals are demanded. Also, better ease and convenience of use are required of these electronic appliances. In this respect, high capabilities and high performance are required of LSIs used in these appliances. While the number of I/Os is increasing as a result of increasingly high integration of LSI chips, there is also a persistent requirement for miniaturization of packages themselves. In order to meet these incompatible demands, development of a semiconductor package adapted for high-density substrate mounting of semiconductor components is in serious demand.
In order to meet such demands, development of a packaging technique, which is referred to as “CSP (Chip Size Package)”, is being undertaken.
With the multi-system-in-a-package technique using the wafer processing, the CSP technique as described above, and a manufacturing apparatus thereof, components such as an insulating film, a copper wiring electrode film, and so forth, are formed on multiple LSIs with vacuum bonding or the like. This enables a bumpless structure thereof, thereby realizing high-speed signal transmission, and also thereby allowing manufacturing of a package with a reduced height.
However, with conventional multi-system-in-a-package techniques such as the manufacturing technique disclosed in Japanese Unexamined Patent Application Publication No. 2002-94247, alignment of multiple chips is performed using a chip mounter, leading to difficulty in improving the alignment precision for mounting the chips. This leads to difficulty in improving the wiring precision dependent upon the chip-alignment precision, resulting in an excessive wiring margin. Accordingly, manufacturing of a high-density integrated semiconductor device, e.g., a multi-system in a package formed of semiconductor integrated circuits such as LSIs and so forth, requires further improved precision of wiring and so forth, which is a remaining technical problem.